VF360 3U VPX Processing Module

The Parsec design team was faced with many challenges over the design phase of this board.

The need for uncompromised signal integrity, high component density, demanding thermal constraints and short timescales, forced the Parsec design team to approach the VF360 design in a different way. Concurrent design amongst teams members, combined with optimal tool use and thorough simulation was required. With operational temperatures that could reach the point of components de-soldering themselves, the team  knew the thermal design of the board and heat sink also needed careful consideration.


Parsec made use of the DxDesigner®/Expedition® tool flow of Mentor Graphics in the design of its flagship 3U VPX card, the VF360. The high-performance processing capability of the Stratix® V FPGA and TMS320C667X DSP processor, combined with a VITA 57 FMC site is packaged in air-cooled and conduction cooled formfactors to provide a powerful and flexible 3U VPX processing card.



The schematic design was implemented using Mentor Graphics’ “DxDesigner®” software, through hierarchical design and making extensive use of “CES” (Constraints Editor System) ensuring all constraints are seamlessly transferred to the Untitled-4PCB design phase. The server based concurrent design capability of DxDesigner® allowed multiple Parsec engineers to simultaneously work on different parts of the schematic. This shortened and simplified the design cycle significantly.


Fast eye simulations were done with HyperlLynx® GHz to ensure signal integrity of all the high-speed serial interfaces on the board. The DDR3 wizard confirmed adherence of the layout and routing to the required DDR3 timing. Layer stack-Untitled-6up and crosstalk simulations were also performed to check EMC levels. Parsec’s experienced digital design team made optimal use of the simulation capability of the HyperlLynx® tool.


The PCB design phase was implemented using Mentor Graphic’s “Expedition®” software. With the use of CES, all constraints including DDR trace length/matching & Differential/Single ended impedances were defined at the schematic stage, thereby eliminating much of the risk normally associated in a board of this complexity. The board is 18 layers, with blind and buried vias to accommodate routing density and improve the thermal characteristics of the board.


Image below illustrates how length tuning to CES requirements was implemented.



Untitled-11The mechanical design was implemented using SolidWorks®, all mechanical constraints were defined and transferred to Expedition® via IGES format, once the components were placed on the board an IGES copy was exported back into SolidWorks® in order to ensure no mechanical conflicts existed. The images to the left, are that of the convection and conduction cooled assemblies.

Untitled-12Thermal transfer to the black anodised aluminium heat-sink was achieved through 5W/m-K thermal pads. Thermal analysis on this unit was achieved through the use of Mentor Graphic’s HyperLynx thermal®.

Thermal analysis of the conduction cooled heat-sink was achieved through the use of Mentor Graphics FloTHERM®


Untitled-14The initial thermal analysis of the module, (taking into account thermal properties of components), indicated that temperatures in excess of 250 °C would be realised. The image left indicates the resultant thermal analysis of the convection module. Taking into account the heat-sink, environmental conditions, board specification (layers, copper weights etc), air flow rate and ambient temperature, the anticipated maximum temperature of the module reduced to 68 °C.